스레드는 <thread> 헤더 파일 안에 C++ 스레드 라이브러리로 만들 수 있다. 스레드가 뭘 할 지 결정하는 방법으로 세 가지가 있다:

1. 함수 객체의 operator()로 표현
2. 람다 표현식 이용
3. 특정 클래스의 인스턴스로 멤버 함수 활용

CPU의 속도는 전력 소모량과 열에 의해 빠르기에 한계를 가지고 있다. 만약 CPU가 병행하게 작동한다면, 수행 기간은 이전보다 더 짧아질 것이다. 요즘은 듀얼과 쿼드라 코어 프로세스가 보편적으로 사용된다. 심지어, 12, 18 그리고 18 코어 프로세서도 도입되고 있다.

멀티-스레드 프로세서는 2개 이상의 프로세스 유닛을 가진 프로세서이다. 프로세스 유닛은 개별 CPU를 가진 프로세서 칩이나 코어라는 이름의 CPU일 수 있다. 멀티-프로세서는 최근 널리 사용되고 있다. 따라서 멀티-스레드 프로그래밍은 최신 기술이다.

Here, the mothods not yet adopted to this project are written.

It seems that the cluster shape can be specified with 5 species. Each cluster shape species are named as ordinary, long, multi, toothless and opacity.

Garfield simulation is made for testing silicon detector or gas chamber like TPC against to high energy particles from colliding point. A biggest difference between high and low energy incident particle is energy loss. The high energy particles lose few energy, it means that decreasing momentum of particle is ignorable. The alpha particle from 241Am, however, deposit all of their energy to silicon detector and stop there.

Shapes for doubled cluster analysis

Distance: 3mm Incident Angle: 0deg

0.0VBB

It is stoped because the pulse shape is broken because of large deposit energy by 241Am.

Some seed signals have extremely high signal value around 120mV.

Same proximity board & Different Chips

Pulse

Pulse signal

Matrix and seed signal

Improtant plots

Gain control plot

Bellows

Bellows

The pixel information stored as a form of array which length is 2. std::array<int,2> is used for this array. For reduce search time, the cluster information is stored into two different variable-length arraies, std::vector<std::array<int,2>>. These arraies are named as clusteredEvent and suspiciousCluster. First an cluster candidate is generated, it is appended to suspiciousCluster.

• Hitmap

General info

General Info

Because assuming the cluster size of ALPIDE by particle is related to deposit energy by particle, it is important to calculate deposit energy from initial kinetic energy from source. In this projects, $^{241}Am$ and $^{90}Sr$ are used for obtaining alpha, beta and gamma particles. But there are many factors to disturb knowing exact informations like impurities, so the manufacture process should be researched for calculate impurities effect.

Setting and simulation results are shown. The specific explanation is located the end of this page.

ALPIDE

ALPIDE is short form of ALice PIxel Detector.

• Dimension: $1.5\mathrm{cm} \times 3.0\mathrm{cm}$
• Pixels: $512(row) \times 1024(column)$
• Pixel pitches
  • Old: $28\mathrm{\mu m} \times 28 \mathrm{\mu m}$

Reference Paper

• ALPIDE, the Monolithic Active Pixel Sensor for the ALICE ITS upgrade

Schematic diagram

개선사항

• 그림에 축 제목 그리기
• 제목 Lossed->Lost

클러스터 사이즈는 아직 설명하지 못하는 부분이 많다. 따라서 이 문서는 계속 업데이트 되어야 할 것이다.

페르미 준위($E_F$)는 절대영도에서 바닥부터 전자를 채웠을 때 가장 높은 에너지 준위를 뜻한다. 예를 들어 3차원 공간에서 자유 전자의 페르미 기체를 가정해보자. 슈뢰딩거 방정식은 다음과 같다.

<!–

개선사항

• 오차그래프 그리기

• Hitmap
  • Am-241 방사선원을 차폐하지 않은 경우 (alpha + gamma)

• Hitmap
  • Am-241 방사선원을 차폐하지 않은 경우 (alpha + gamma)

• Hitmap
  • Am-241 방사선원을 차폐하지 않은 경우 (alpha + gamma)

A4W975R7

New

There are 2 types of noises, continuous noise, and coincidence noise. The continuous noise is a pixel fired mostly in an event. It can be removed easily by maksing the pixel. But coincidence noise occurs randomly on any pixel in ALPIDE. If masking all pixels when they are fired at pedestal, it makes contamination of data. Some of this can be removed by increasing threshold. Although changing threshold, the few coincidence noise can be survived. So masking and unmasking cases are drawn simulatneously.

<!–

APTS initial test

The procedure of initial test of APTS is checking inital performance such likes resistance of chips and electric test. In this section, the methods for measuring resistance and current is shown. And the pulses are given to APTS and checking output signals.

Background

APTS is short form of Analogue Pixel Test Structure. It is designed in ITS3 upgrade project. The main goal of ITS3 upgrade project is decreasing a material budget of inner tracking system. TowerJazz 180nm technology is adopted to a previous tracker, ITS2. In ITS3, new technology with 65nm is choosen, so 65nm thechnology should be tested. Thus the MLR1 chipset was designed for testing the characteristic of 65nm technology. There are many chips in MLR1 such like DPTS, CE65, etc. In this chpter, however, the description focuses on APTS chip.